In the 1980s, the Joint Test Action Group (JTAG) developed a specification for boundary-scan testing that was standardized in 1990 as the IEEE Std. 1149.1-1990. In 1993 a new revision to the IEEE Std. 1149.1 standard was introduced (titled 1149.1a) and it contained many clarifications, corrections, and enhancements. In 1994, a supplement containing a description of the Boundary-Scan Description Language (BSDL) was added to the standard. It was originally designed for testing printed circuit boards using boundary scan, but JTAG testing has expanded to integrated circuits (e.g., processors, controllers, etc.), embedded systems, and other components. Boundary-scan, as defined by the IEEE Std.-1149.1 standard, is an integrated method for testing interconnects on printed circuit boards (PCBs) that are implemented at the integrated circuit (IC) level.
Generally, JTAG testing is implemented via facilities that are built into the device being tested (commonly referred to as the Device under Test or DUT) and an external tester that connects to the DUT via a debug or test port and provides stimulus and control signals to the DUT to implement various tests such as boundary scan tests and receives test result signals and data output from the DUT. This test result data and signals can then be processed to verify the operation of the DUT. Typically, devices such as processors or Systems on a Chip (SoCs) have pins that are electronically connected to the JTAG tester via a debug port coupled to a socket the processor is mounted in. Similar debug ports may be provided at the board level, although there are instances where JTAG is used only for design debug and the production boards do not include a debug port and/or debug port connector or other type of JTAG interface.
Recently, there has been an increased emphasis on power reduction in computer devices and systems. Although applicable to both desktop computers and servers, reduction of power is particularly important for mobile platforms including laptop, notebooks, ultrabooks, tablets, mobile phones, etc. Under traditional processor and SoC designs, all input/output (I/O) interfaces and associated logic and ports (as applicable) are brought up to an operating state when the processor/SoC is initialized. Notably, each I/O interface/port consumes some base level of power whether or not it is in use. In consideration of this, recent SoC designs have provisions for disabling I/O interface and ports when not in use. Moreover, selected I/O interfaces and ports may not power up until they are needed, thus facilitating on-demand functionality. Under one approach, this functionality is facilitated through use of internal voltage regulators (referred to as Low Drop Out (LDO) circuits) that are turned on by a power management unit using firmware or other means. However, if firmware is required to turn on the I/Os to enable boundary scan testing, the scheme is not compliant with current IEEE Std. 1149.1 methods of enabling the boundary scan. In addition, since boundary scan of the I/Os requires a complete circuit path through each I/O's boundary scan cell, the boundary scan chain is broken when an I/O is not powered.